A DMOS (Double Diffused MOS) transistor is a type of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that uses diffusion to form the transistor region. DMOS transistors are typically employed as power transistors for high voltage power integrated circuits. DMOS transistors provide high current per unit area where low forward voltage drops are required.
One particular type of DMOS transistor is a so-called trench DMOS transistor in which the channel is formed vertically and the gate is formed in a trench extending between the source and drain. The trench, which is lined with a thin oxide layer and filled with polysilicon (i.e., polycrystalline silicon), allows less constricted current flow and thereby provides lower values of specific on-resistance. Examples of trench DMOS transistors are disclosed in U.S. Pat. Nos. 5,072,266, 5,541,425, and 5,866,931, the disclosures of which are hereby incorporated by reference.
FIG. 1 illustrates half of a hexagonally shaped prior art trench DMOS structure 21. The structure includes an n+ substrate 23, upon which is grown a lightly doped n epitaxial layer 25 of a predetermined depth depi. Within the epi layer 25, p body region 27 (p, p+) is provided. In the design shown, the p body region 27 is substantially planar (except in a central region), lying a distance dmin below the top surface of the epi layer. Another layer 28 (n+) overlying most of the p body region 27 serves as source. A series of hexagonally shaped trenches 29 are provided in the epitaxial layer, opening toward the top and having a predetermined depth dtr. The trenches 29 are typically lined with oxide and filled with conductive polysilicon, forming the gate for the DMOS device. The trenches 29 define cell regions 31 that are also hexagonally shaped in horizontal cross-section. Within the cell region 31, the p body region 27 rises to the top surface of the epi layer and forms an exposed pattern 33 in a horizontal cross section at the top surface of the cell region 31. In the specific design illustrated, the p+ central portion of the p body region 27 extends to a depth dmax below the surface of the epi layer that is greater than the trench depth dtr for the transistor cell so that breakdown voltage is away from the trench surface and into the bulk of the semiconductor material.
A typical DMOS device includes numerous individual DMOS transistor cells 31 that are fabricated in parallel within a single chip (i.e., a section of a semiconductor wafer). Hence, the chip shown in FIG. 1 contains numerous hexagonal-shaped cells 31 (portions of five of these cells are illustrated). Cell configurations other than hexagonal configurations are commonly used, including square-shaped configurations. In a design like that shown in FIG. 1, the substrate region 23 acts as a common drain for all of the individual DMOS transistor cells 31. Although not illustrated, all the sources for the DMOS cells 31 are typically shorted together via a metal source contact that is disposed on top of the n+ source regions 28. An insulating region, such as borophosphosilicate glass (not shown) is typically placed between the polysilicon in the trenches 29 and the metal source contact to prevent the gate regions from being shorted with the source regions. Consequently, to make gate contact, the polysilicon within the trenches 29 is typically extended into a termination region beyond the DMOS cells 31, where a metal gate contact is provided on the polysilicon. Since the polysilicon gate regions are interconnected with one another via the trenches, this arrangement provides a single gate contact for all the gate regions of the device. As a result of this scheme, even though the chip contains a matrix of individual transistor cells 31, these cells 31 behave as a single large transistor.
Unfortunately, in a prior art design like that described above, contact with the drain is made from the underside of the chip, while source and gate contact is made from the topside of the chip. As a result, it is typically necessary to dispose the chip within a package that provides source, drain and gate contacts on a single surface.